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| (00,&52(/(&7521,&0$5,16$ ? em microelectronic-marin sa, 2/99, rev. b/243 1 EM6605 - 4 bit microcontroller features low power - typical 4.0a active mode - typical 2.5a standby mode - typical 0.3a sleep mode @ 1.8v, 32khz, 25 c low voltage - 1.8 to 5.5v rc oscillator 30 - 300khz buzzer - three tone rom - 2k 16 (mask programmed) ram - 96 4 (user read/write) 2 clocks per instruction cycle risc architecture 4 software configurable 4-bit ports up to 16 inputs (4 ports) up to 12 outputs (3 ports) serial (output) write buffer - swb voltage level detection analogue watchdog timer watchdog 8 bit timer / event counter internal interrupt sources (timer, event counter, prescaler) external interrupt sources (porta + portc) description the em66xx series is an advanced single chip low cost, mask programmed cmos 4-bit microcontroller. it contains rom, ram, watchdog timer, oscillation detection circuit, combined timer / event counter, prescaler, voltage level detector and a number of clock functions. its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. the em66xx series is manufactured using ems advanced low power cmos process. typical applications sensor interfaces domestic appliances security systems automotive controls tv & audio remote controls measurement equipment r/f and ir. control figure 1.architecture figure 2.pin configuration
EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 2 EM6605 at a glance power supply - low voltage, low power architecture including internal voltage regulator - 1.8v ... 5.5 v battery voltage - 4.0 $lqdfwlyhprgh - 2.5 $lqvwdqge\prgh - 0.3 $lqvohhsprgh @ 1.8v, 32khz, 25 c - rc oscillator from 30-300khz ram - 96 x 4 bit, direct addressable rom - 2048 x 16 bit metal mask programmable cpu - 4 bit risc architecture - 2 clock cycles per instruction - 72 basic instructions main operating modes and resets - active mode (cpu is running) - standby mode (cpu in halt) - sleep mode (no clock, reset state) - initial reset on power-on (por) - external reset pin - watchdog timer (time-out) reset - oscillation detection watchdog reset - reset with input combination on porta (metal option) supply voltage level detector - 3 software selectable levels defined by user between 1.9v and 4.5v) - busy flag during measure - active only on request during measurement to reduce power consumption 4-bit input porta - direct input read - debounced or direct input selectable (reg.) - interrupt request on inputs rising or falling edge, selectable by register. - pull-down or none, selectable by met. mask - software test variables for conditional jumps - pa3 input for the event counter - reset with input combination on porta (metal option) 4-bit input/output portb - separate input or output selection by register - pull-up, pull-down or none, selectable by metal mask if used as input - buzzer output on pb0 4-bit input/output portc - input or output port as a whole port - debounced or direct input selectable (reg.) - interrupt request on inputs rising or falling edge, selectable by register. - pull-up, pull-down or none, selectable by metal mask if used as input - cmos or n-channel open drain mode 4-bit input/output portd - input or output port as a whole port - pull-up, pull-down or none, selectable by metal mask if used as input - cmos or n-channel open drain mode - serial write buffer clock and data output serial (output) write buffer - max. 256 bits long clocked with ck[15]/ck[14]/ck[12]/ck[11] = 16/8/2/1khz - automatic send mode - interactive send mode : interrupt request when buffer is empty rcoscillator - rc oscillator with an external resistor for frequency adjustment in range from 30khz to 300khz - production tolerance 20% - temperature toll. 5%, -20 c EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 4 table 1. pin description pin number pin name function remarks 1 port a, 0 input 0 port a interrupt request; tvar 1 2 port a, 1 input 1 port a interrupt request; tvar 2 3 port a, 2 input 2 port a interrupt request; tvar 3 4 port a, 3 input 3 port a interrupt request; event counter input 5 port b, 0 input / output 0 port b buzzer output 6 port b, 1 input / output 1 port b 7 port b, 2 input / output 2 port b 8 port b, 3 input / output 3 port b 9 test test input terminal for em test purpose only 10* rcin rc external resistor typically 120kohm - 330kohm 11 rcout/nc rc output frequency connect it at vss - ground 12 vss negative power supply terminal 13 stb/rst strobe / reset status c reset state + port b, c, d, write 14 port c, 0 input / output 0 port c interrupt request 15 port c, 1 input / output 1 port c interrupt request 16 port c, 2 input / output 2 port c interrupt request 17 port c, 3 input / output 3 port c interrupt request 18 port d, 0 input / output 0 port d swb serial clock output 19 port d, 1 input / output 1 port d swb serial data output 20 port d, 2 input / output 2 port d 21 port d, 3 input / output 3 port d 22 reset reset terminal active high (internal pull-down) 23 vreg internal voltage regulator needs typ. 100nf capacitor tw. vss 24 vdd positive power supply terminal figure 3.typical configuration rcin node is hi impedance node and the connection towards rext to fix the frequency should be as short as possible. treat this node as quartz node. for vdd less then 2.0v it is recommended that vdd is connected directly to vreg for vdd>2.2v then the configuration shown in fig.3 should be used. EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 5 1. operating modes the EM6605 has two low power dissipation modes: standby and sleep. figure 4 is a transition diagram for these modes. 1.1. standby mode executing a halt instruction puts the EM6605 into standby mode. the voltage regulator, oscillator, watchdog timer, interrupts and timer/event counter are operating. however, the cpu stops since the clock related to instruction execution stops. registers, ram, and i/o pins retain their states prior to standby mode. standby is cancelled by a reset or an interrupt request if enabled. table 2 : shows the state of the EM6605 functions in standby and sleep modes. 1.2. sleep mode writing to the sleep bit in the intrq register puts the EM6605 in sleep mode. the oscillator stops and most functions of the EM6605 are inactive. to be able to write the sleep bit, the slmask bit must first be set to 1. in sleep mode only the voltage regulator and reset input are active. the ram data integrity is maintained. sleep mode may be cancelled only by a reset at the terminal pin of the EM6605. the reset must be high for at least 2sec. figure 4.mode transition diagram table 2.standby and sleep activities function standby sleep oscillator active stopped instruction execution stopped stopped registers and flags retained reset interrupt functions active stopped ram retained retained timer/counter active stopped watchdog active stopped i/o pins active high-z or retained supply vld stopped stopped reset pin active active due to the cold start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee that the oscillator has started correctly. during this time the circuit is in reset and the strobe output stb/rst is high. waking up from sleep mode clears the sleep flag but not the slmask bit. by reading slmask one can therefore determine if the EM6605 was powered up ( slmask = 0), or woken from sleep mode ( slmask = 1). 2. power supply the EM6605 is supplied by a single external power supply between vdd and vss, the circuit reference being at vss (ground). a built-in voltage regulator generates vreg providing regulated voltage for the oscillator and internal logic. output drivers are supplied directly from the external supply vdd. a typical connection configuration is shown in figure 3. for vdd less then 2.0v it is recommended that vdd is connected directly to vreg for vdd>2.2v then the configuration shown in fig.3 should be used. EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 6 3. reset to initialise the EM6605, a system reset must be executed. there are four methods of doing this: (1) initial reset from the oscillation detection circuit. (2) external reset from the reset pin. (3) external reset by simultaneous high input to terminals pa0..pa3. (combinations defined by metal option) (4) watchdog reset (software option). during any of these resets the stb/rst output pin is high. figure 5.system reset generation 3.1. oscillation detection circuit at power on, the built-in voltage regulator starts to follow the supply voltage until vdd becomes higher than vreg. since it is vreg which supplies the oscillator and this needs time to stabilise, power-on-reset with the oscillation detection circuit therefore counts the first 64 or 128 oscillator clocks after power-on and holds the system in reset. the system will consequently remain in reset during cold start time - t cost (see table 6) for at least 2msec or 4msec second after power up from the 32khz clock (*f1) - see table 6 for frequencies. after power up the analogue watchdog circuit monitors the oscillator. if it stops for any reason other then sleep mode, then a reset is generated and the stb/res pin is driven high. 3.2. reset pin during active or standby mode the reset terminal has a debouncer to reject noise and therefore must be active high for at least 2ms = t debs / 16ms = t debl (*f1) (clk = 32khz) - software selectable by debck in cirqd register. (see / table 32) at power on, or when cancelling sleep mode, the debouncer is not active and so reset must satisfy the filter time constant (typ. 1sec) such that the reset must be active high for at least 2sec. EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 7 3.3. input port (pa0..pa3) reset with a mask option it is possible to choose from four porta reset combinations. the selected ports must be simultaneously high for at least 2ms = t debs / 16ms = t debl (*f1) (clk = 32khz) due to the presence of debouncers. note also, that reset with port a is not possible during sleep mode. below are the combinations of port a (pa0..pa3) inputs which can be used to generate a reset. they can be selected by metal ? porta reset ? mask option described in chapter 14. table 3.porta inputs reset options function opt. code option a no inputs reset ra0 option b reset = pa0 * pa1 ra1 option c reset = pa0 * pa1 * pa2 ra2 option d reset = pa0 * pa1 * pa2 * pa3 ra3 3.4. watchdog timer reset the watchdog timer reset is a software option and if used it will generate a reset if it is not cleared. see section 5. watchdog timer for details. table 4.watchdog-timer option watchdog function nowd bit in option register without watchdog time-out reset 1 with watchdog time-out reset 0 3.5. cpu state after reset reset initialises the cpu as shown in the table below. table 5.initial value after reset name bits symbol initial value program counter 0 12 pc0 $000 (as a result of jump 0) program counter 1 12 pc1 undefined program counter 2 12 pc2 undefined stack pointer 2 sp sp(0) selected index register 7 ix undefined carry flag 1 cy undefined zero flag 1 z undefined halt 1 halt 0 instruction register 16 ir jump 0 periphery registers 4 see peripheral memory map EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 8 4. oscillator a built-in rc oscillator circuit generates the system operating clock ck[16] for the cpu and peripheral circuits with the help of an externally connected resistor (between rcin and vss) which determins the frequency and a capacitor for better frequency stability. the oscillator circuit is supplied by the regulated voltage, vreg. in sleep mode the oscillator is stopped. note: because the frequency can be selected by the user with an external resistor in a range from 30khz - 130khz (lf range) or 100khz - 330khz (hf range) there is a table of corresponding frequencies for 3 different system clock frequencies. from now on besides each freq. name ck[x] there will be also an example for 32 768 hz system clock marked by (*f1) to indicate first - lowest frequency. table 6. prescaler clock name definitions and frequency examples function name frequency 1 (*f1) frequency 2 (*f2) frequency 3 (*f3) system clock ck[16] 32 768 hz 131 072 hz 327 680 hz sys. clock / 2 ck[15] 16 348 hz 65 536 hz 163 480 hz sys. clock / 4 ck[14] 8 192 hz 32 768 hz 81 920 hz sys. clock / 8 ck[13] 4 096 hz 16 348 hz 40 960 hz sys. clock / 16 ck[12] 2 048 hz 8 192 hz 20 480 hz sys. clock / 32 ck[11] 1 024 hz 4 096 hz 10 240 hz sys. clock / 64 ck[10] 512 hz 2 048 hz 5 120 hz sys. clock / 128 ck[9] 256 hz 1 024 hz 2 560 hz sys. clock / 256 ck[8] 128 hz 512 hz 1 280 hz sys. clock / 512 ck[7] 64 hz 256 hz 640 hz sys. clock / 1024 ck[6] 32 hz 128 hz 320 hz sys. clock / 2048 ck[5] 16 hz 64 hz 160 hz sys. clock / 4096 ck[4] 8 hz 32 hz 80 hz sys. clock / 8192 ck[3] 4 hz 16 hz 40 hz sys. clock / 16384 ck[2] 2 hz 8 hz 20 hz sys. clock / 32768 ck[1] 1 hz 4 hz 10 hz debouncer - long t debl 16 msec 4 msec 1.6 msec debouncer - short t debs 2 msec 0.5 msec 0.2 msec cold start delay t cost ~ 2 msec ~ 1 msec ~ 0.7 msec 1st buzzer freq. ck[buz1] 1 024 hz 4 096 / *512 hz 10 240/ *1 280 hz 2nd buzzer freq. ck[buz2] 2 048 hz 8 192 / *1 024 hz 20 480/ *2 560 hz 3rd buzzer freq. ck[buz3] 2 667 hz 10 667 hz 26 667 hz buzzer frequencies for hi frequency system clock have metal option 4.1. prescaler the input to the prescaler is the system clock signal. the prescaler consists of a fifteen element divider chain which delivers clock signals for the peripheral circuits such as the timer/counter, buzzer, i/o debouncers and edge detectors, as well as generating prescaler interrupts. table 7.prescaler interrupt source interrupt frequency psf1 psf0 mask(no interrupt) 0 0 ck[1] (1hz *f1 ) 01 ck[4] (8hz *f1 ) 10 ck[6] (32hz *f1 ) 11 the frequency of prescaler interrupts is software selectable, as shown in table 7 EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 9 table 8.prescaler control register - presc bit name reset r/w description 3 mtim 0 r/w timer/counter interrupt mask 2 prst - r/w prescaler reset 1 psf1 0 r/w prescaler interrupt select 1 0 psf0 0 r/w prescaler interrupt select 0 5. watchdog timer if for any reason the cpu crashes, then the watchdog timer can detect this situation and output a system reset signal. this function can be used to detect program overrun. for normal operation the watchdog timer must be reset periodically by software at least once every three seconds (*f1) (clk = 32khz) or a system reset signal is generated to cpu and periphery. the watchdog is active during standby. the watchdog reset function can be deactivated by setting the nowd bit to 1 in the option register. in worst case because of prescaler reset function wd time-out can come down to 2 seconds. the watchdog timer is reset by writing 1 to the wdrst bit. writing 0 to wdrst has no effect. the watchdog timer also operates in standby mode. it is therefore necessary to reset it if this mode continues for more than three seconds (*f1) . one method of doing this is to reset it with the prescaler ck[1] interrupt (1hz *f1 such, that the watchdog is reset every second). table 9.watchdog register - wd bit name reset r/w description 3 wdrst - r/w watchdog timer reset 2 slmask - r/w sleep mask bit 1 wd1 0r wd timer data ck[1]/4 (1/4hz *f1 ) 0 wd0 0r wd timer data ck[1]/2 (1/2 hz *f1 ) EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 10 6. input and output ports the EM6605 has four independent 4-bit ports, as shown in table 9. table 10.input / output ports overview port mode mask options function(s) pa(0:3) input pull-up/down ( * ) debouncer ( * ) + or - irq edge reset combination input interrupt software test variable pa3 input for event counter reset input(s) pb(0:3) individual input or output nch open drain output pull-up/down on input input or output pb0 for buzzer output pc(0:3) port input or output pull-up/down ( * ) + or - irq edge ( * ) debouncer nch open drain output input or output port interrupt pd(0:3) port input or output pull-up/down on input nch open drain output input or output port pd0 -swb serial clock output pd1 -swb serial data output ( * ) some options can be set also by option register . table 11.option register - option bit name reset r/w description 3 irqedger 0 r/w rising edge interrupt for porta&c 2 debpcn 0 r/w portc without/with debouncer 1 debpan 0 r/w porta without/with debouncer 0 nowd 0 r/w watchdog timer off irqedger - valid for both porta and portc input interrupt edge. at reset it is cleared to 0 selecting the falling edge at the input as the interrupt source. when set to 1 the rising edge is active. (option 2 on fig.6 and fig.8) debpan - by default after reset it is 0 enabling the debouncers on whole porta. writing it to 1 removes the debouncers from the porta. (option 2 on fig.6) debpcn - by default after reset it is 0 enabling the debouncers on whole portc. writing it to 1 removes the debouncers from the portc. (option 2 on fig.8) nowd - by default after reset it is 0 = watchdog timer is on. writing it to 1 removes the watchdog timer. 6.1. porta the EM6605 has one four bit general purpose input port. each of the input port terminals pa3..pa0 has an internal pull-up/down resistor which can be selected with mask options. port information is read directly from the pin into a register. on inputs pa0, pa1, pa2 and pa3 debouncers for noise rejection are added by default. for interrupt generation, one can choose between either direct input or debounced input. with the debpan bit at 0 in the option register all the porta inputs are debounced and with the debpan bit at 1 none of the porta inputs are debounced. with the debouncer selected the input must be stable during two rising edges of ck[11] or ck[8] clocks (1024hz or 128hz (*f1) at 32khz). this corresponds to a worst case of t debs or t debl shown in table 6. porta terminals pa0, pa1 and pa2 are also used as input conditions for conditional software branches as shown on the next page: EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 11 debounced pa0 is connected to cpu testvar1 debounced pa1 is connected to cpu testvar2 debounced pa2 is connected to cpu testvar3 figure 6.port a additionally, pa3 can also be used as the input terminal for the event counter (see section 8). the input port pa(0:3) also has individually selectable interrupts. each port has its own interrupt mask bit in the mporta register. when an interrupt occurs inspection of the irqpa and the intrq registers allows the source of the interrupt to be identified. the irqpa register is automatically cleared by a reset, by reading the register. reading irqpa register also clears the intpa flag in intrq register. at initial reset the mporta is set to 0, thus disabling any input interrupts. see also section 9 for further details about the interrupt controller. 6.2. porta registers table 12.porta input status register - porta bit name reset r/w description 3 pa3 - r pa3 input status 2 pa2 - r pa2 input status 1 pa1 - r pa1 input status 0 pa0 - r pa0 input status table 13.porta interrupt request register - irqpa bit name reset r/w description 3 irqpa3 0 r input pa3 interrupt request flag 2 irqpa2 0 r input pa2 interrupt request flag 1 irqpa1 0 r input pa1 interrupt request flag 0 irqpa0 0 r input pa0 interrupt request flag table 14.porta interrupt mask register - mporta bit name reset r/w description 3 mpa3 0 r/w interrupt mask for input pa3 2 mpa2 0 r/w interrupt mask for input pa2 1 mpa1 0 r/w interrupt mask for input pa1 0 mpa0 0 r/w interrupt mask for input pa0 EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 12 6.3. portb the EM6605 has one four bit general purpose i/o port. each bit pb(0:3) can be separately configured by software to be either input or output by writing to the corresponding bit of the cioportb control register. the portb register is used to read data when in input mode and to write data when in output mode. on each terminal pull-up/down resistor can be selected by metal option when input. input mode is set by writing 0 to the corresponding bit in the cioportb register. this results in a high impedance state with the status of the pin being read from register portb. output mode is set by writing 1 to the corresponding bit in the cioportb register. consequently the output terminal follows the status of the bits in the portb register. at initial reset the cioportb register is set to 0, thus setting the port to an input. additionally, pb0 can also be used as a three tone buzzer output. for details see section 7. 6.4. portb registers table 15.portb input status register - portb bit name reset r/w description 3 pb3 - r/w pb3 i/o data 2 pb2 - r /w pb2 i/o data 1 pb1 - r/w pb1 i/o data 0 pb0 - r /w pb0 i/o data table 16.portb input/output control register - cioportb bit name reset r/w description 3 ciopb3 0 r/w pb3 input/output select 2 ciopb2 0 r/w pb2 input/output select 1 ciopb1 0 r/w pb1 input/output select 0 ciopb 0 0 r/w pb0 input/output select figure 7.port b if metal mask option 5y (input blocked when output) is used and the port is declared as the output ( cioportb = 1111b) the real port information cannot be read directly. in this case no direct logic operations (like and portb ) on output ports are possible. this logic operation can be made if an image of the port saved in the ram which we store after on the output port. this is valid for portb, portc and portd when declared as output and the metal option 5y is used. in the case of metal option 5n selected direct logic operations on output ports are possible. if metal mask option 6y (output hi-z in sleep mode) the active output will go tristate when the circuit goes into sleep mode. in the case of 6n output stay active also in the sleep mode. EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 13 6.5. portc this port can be configured as either input or output (not bitwise selectable). when in input mode it implements the identical interrupt functions as porta. the portc register is used to read data when input mode and to write data when in output mode. input mode is set by writing 0 to the i/o control bit ciopc in register cpiob and the input becomes high impedance. on each terminal pull-up/down resistor can be selected by metal option which are active only when selected as input. the output mode is selected by writing 1 to ciopc bit, and the terminal follows the bits in the portc register. when portc is used as an input, interrupt functions as described for porta can be enabled. input to the interrupt logic can be direct or via a debounced input. with the debpcn bit at 0 in the option register all the portc inputs are debounced and with the debpcn bit at 1 none of the portc inputs are debounced. mportc is the interrupt mask register for this port and irqpc is the portc interrupt request register. see also section 9. by writing the pa&c bit in the cpiob data register it is possible to combine porta and portc interrupt requests (logic and) as shown in table 16. at initial reset, the cpioc control register is set to 0, and the port is in input mode. the mportc register is also set to 0, therefore disabling interrupts. table 17.ports a&c interrupt request irqpa irqpc pa&c request to cpu 00xno 010yes 100yes 110yes 011no 101no 111yes 6.6. portc registers table 18.portc input/output register - portc bit name reset r/w description 3 pc3 - r/w pc3 i/o data 2 pc2 - r /w pc2 i/o data 1 pc1 - r/w pc1 i/o data 0 pc0 - r /w pc0 i/o data table 19.portc interrupt request register - irqpc bit name reset r/w description 3 irqpc3 0 r input pc3 interrupt request flag 2 irqpc2 0 r input pc2 interrupt request flag 1 irqpc1 0 r input pc1 interrupt request flag 0 irqpc0 0 r input pc0 interrupt request flag table 20.portc interrupt mask register - mportc bit name reset r/w description 3 mpc3 0 r/w interrupt mask for input pc3 2 mpc2 0 r/w interrupt mask for input pc2 1 mpc1 0 r/w interrupt mask for input pc1 0 mpc0 0 r/w interrupt mask for input pc0 EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 14 figure 8.port c for portc and portd metal options 5y/n and 6y/n are port-wise (for the whole port). for portb these options are bit-wise (every terminal can have individual mask set-up for the options 5y/n and 6y/n ). EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 15 6.7. portd the EM6605 has one all purpose i/o port similar to portc but without interrupt capability. the portd register is used to read input data when an input and to write output data for output. the input line can be pulled down (metal option) when the port is used as input. input mode is set by writing 0 to the i/o control bit ciopd in register cpiob , and the terminal becomes high impedance. on each terminal pull-up/down resistor can be selected by metal option which are active only when selected as input. output mode is set by writing 1 to the control bit ciopd. consequently, the terminal follows the status of the bits in the portd register. if serial write buffer function is enabled pd0 and pd1 terminals of portd output serial clock and serial data respectively. for details see 11.0 serial write buffer . 6.8. portd registers table 21.portd input/output register - portd bit name reset r/w description 3 pd3 0 r/w pd3 i/o data 2 pd2 0 r/w pd2 i/o data 1 pd1 0 r/w pd1 i/o data 0 pd0 0 r/w pd0 i/o data table 22.ports control register - cpiob bit name reset r/w description 3 - - r/w not used 2 ciopd 0 r/w i/o portd select 1 ciopc 0 r/w i/o portc select 0 pa&c 0r/w logical and of irqs from porta & portc figure 9.port d EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 16 7. buzzer the EM6605 has one 50% duty cycle output with three different frequencies which can be used to drive a buzzer. i/o terminal pb0 is used for this function when the buzzer is enabled by setting the buen bit to 1 . table 23 below shows how to select the frequency by writing to the bcf1 and bcf0 control flags in the beep register. after writing to the buzzer control register beep, the chosen frequency (or silence) is selected immediately. with the buen bit set to 1, the selected frequency is output at pb0. when the buen is set to 0 pb0 is used as a normal i/o terminal of portb. the buen bit has a higher priority over the i/o control bit ciopb0 in the cioportb register. table 23.buzzer frequency selection tone frequency bcf1 bcf0 silence 0 0 ck[buz1] = ck[11] or ck[8] by metal option (1024 hz *f1 ) 01 ck[buz2] = ck[12] or ck[10] by metal option (2048 hz *f1 ) 10 ck[buz3] (2667 hz *f1 ) 11 7.1. buzzer register table 24.buzzer control register - beep bit name reset r/w description 3 timen 0 r/w timer/counter enable 2 buen 0 r/w buzzer enable 1 bcf1 0 r/w buzzer frequency control 0 bcf0 0 r/w buzzer frequency control EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 17 8. timer/event counter the EM6605 has a built-in 8 bit auto-reload timer/event counter that takes an input from either the prescaler or port pa3. if the timer/event counter counts down to $00 the interrupt request flag intte is set to 1. if the timer/event counter interrupt is enabled by setting the mask flag mtimc set to 1, then an interrupt request is generated to the cpu. see also section 9. if used as an event counter, pulses from the pa3 terminal are input to the event counter. see figure 10 and tables 29 and 30 on the next page for pa3 source selection (debounced or not, rising/falling edge). by default rising and debounced pa3 input is selected. the timer control register timctr selects the auto-reload function and input clock source. at initial reset this bit is cleared to 0 selecting no auto-reload. to enable auto-reload timauto must be set to 1. the timer/counter can be enabled or disabled by writing to the timen control bit in the beep register. at initial reset it is cleared to 0. when used as timer, it is initialised according to the data written into the timer load/status registers ltimls (low 4 bits) and htimls (high four bits). the timer starts to count down as soon as the ltimls value is written. when loading the timer/event counter registers the correct order must be respected: first, write either the control register timctr or the high data nibble htimls . the last register written should be the low data nibble ltimls . during count down, the timer can always be reloaded with a new value, but the high four bits will only be accepted during the write of the low four bits. in the case of the auto-reload function, the timer is initialised with the value of the load registers ltimls and htimls . counting with the auto-reload function is only enabled during the write to the low four bits, (writing teauto to 1 does not start the timer counting down with the last value in the timer load registers but it waits until a new ltimls load). the timer counting to $00 generates a timer interrupt event and reloads the registers before starting to count down again. to stop the timer at any time, a write of $00 can be made to the timer load registers, this sets the timauto flag to 0. if the timer is stopped by writing the timen bit to 0, the timer status can be read. the current timer status can be always obtained by reading the timer registers ltimls and htimls . for proper operation read ordering should be respected such that the first read should be of the ltimls register followed by the htimls register. example: to have continuos 1sec timer irq with 128hz one has to write 128dec (80hex) in timer registers with auto-reload. using the timer/counter as the event counter allows several possibilities: 1.) firstly, load the number of pa3 input edges expected into the load registers and then generate an interrupt request when counter reaches $00. 2.) the second is to write timer/counter to $ff, then select the event counter mode, and lastly enable the event counter by setting the timen bit to 1, which starts the count. because the counter counts down, a binary complement has to be done in order to get the number of events at the pa3 input. 3) another option is to use the timer/counter in conjunction with the prescaler interrupt, such that it is possible to count the number of the events during two consecutive ck[6], ck[4], ck[1], (32hz, 8hz or 1hz *f1 ) prescaler interrupts. figure 10.timer / event counter EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 18 table 25 shows the selection of inputs to the timer/event counter table 25.timer clock selection tec2 tec1 tec0 timer/counter clock source 0 0 0 not active 00 1 ck[12] from prescaler; ( 2048 hz *f1 ) 01 0 ck[10] from prescaler; ( 512 hz *f1 ) 01 1 ck[8] from prescaler; ( 128 hz *f1 ) 10 0 ck[6] from prescaler; ( 32 hz *f1 ) 10 1 ck[4] from prescaler; ( 8 hz *f1 ) 11 0 ck[1] from prescaler; ( 1 hz *f1 ) 1 1 1 pa3 input terminal (see tables 29 and 30) 8.1. timer/counter registers table 26.timer control register - timctr bit name reset r/w description 3 timauto 0 r/w timer/counter auto reload 2 tec2 0 r/w timer/counter mode 2 1 tec1 0 r/w timer/counter mode 1 0 tec0 0 r/w timer/counter mode 0 table 27.low timer load/status register - ltimls (4 low bits) bit name reset r/w description 3 tl3/ts3 0 r/w timer load/status bit 3 2 tl2/ts2 0 r/w timer load/status bit 2 1 tl1/ts1 0 r/w timer load/status bit 1 0 tl0/ts0 0 r/w timer load/status bit 0 table 28.high timer load/status register - htimls (4 high bits) bit name reset r/w description 3 tl7/ts7 0 r/w timer load/status bit 7 2 tl6/ts6 0 r/w timer load/status bit 6 1 tl5/ts5 0 r/w timer load/status bit 5 0 tl4/ts4 0 r/w timer load/status bit 4 table 29.pa3 counter input selection register - pa3cnt bit name reset r/w description 3 - - - empty 2 - - - empty 1 - - - empty 0 pa3cntin 0 r/w pa0 input status table 30.pa3 counter input selection pa3cntin debpan irqedger counter source 0 x x pa3 debounced rising edge 1 0 0 pa3 debounced falling edge 1 0 1 pa3 debounced rising edge 1 1 0 pa3 not debounced falling edge 1 1 1 pa3 not debounced rising edge x ( dont care) EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 19 9. interrupt controller the EM6605 has six different interrupt sources, each of which is maskable. these are: external (3) - porta pa3..pa0 inputs - portc pc3..pc0 inputs - combined and of porta * portc internal (3) - prescaler ck[6] / ck[4] / ck[1] (32hz / 8hz / 1hz *f1 ) - timer/event counter - swb in interactive mode for an interrupt to the cpu to be generated, the interrupt request flag must be set ( int xx), and the corresponding mask register bit must be set to 1 ( m xx), the general interrupt enable flag ( inten ) must also be set to 1. the interrupt request can be masked by the corresponding interrupt mask registers mport x for each input interrupt and by psf0 ,psf1 and mtim for internal interrupts. at initial reset the interrupt mask bits are set to 0. inten bit is set automatically to 1 by halt instruction except when starting the automatic swb transfer (see serial write buffer ( swb ) chapter 11) the cpu is interrupted when one of the interrupt request flags is set to 1 in register intrq and the inten bit is enabled in the control register cirqd. intte and intpr flags are cleared automatically after a read of the intrq register. the other two interrupt flags intpa (irq from porta) and intpc (irq from portc) in intrq register are cleared only after reading the corresponding port interrupt request registers i rqpa and irqpc . at the power on reset and in sleep mode the inten bit is also set to 0 therefore not allowing any interrupt requests to the cpu until it is set to 1 by software. since the cpu has only one interrupt subroutine and because the intrq register is cleared after reading, the cpu does not miss any of the interrupt requests which come during the interrupt service routine. if any occur during this time a new interrupt will be generated as soon as the cpu comes out of the current interrupt subroutine. interrupt priority can be controlled through software by deciding which flag in the intrq register should be serviced first. for swb interactive mode interrupt see section 11.0 serial write buffer. 9.1. interrupt control registers table 31.main interrupt request register - intrq (read only)* bit name reset r/w description 3 intpr 0 r prescaler interrupt request 2 intte 0 r timer/counter interrupt request 1 intpc 0 r portc interrupt request 0 intpa 0 r porta interrupt request 2 sleep 0 w* sleep mode flag * write bit 2 only if slmask =1 if the sleep flag is written with 1 then the em6603 goes immediately into sleep mode ( slmask was at 1). EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 20 table 32.register - cirqd bit name reset r/w description 3 reserved - - - 2 reserved - - - 1 debck 0 r/w debouncer clock select (0=t debs : 1=t debl ) * 0 inten 0 r/w enable interrupt to cpu (1=enabled) * see table 6 figure 11.interrupt request generation irq mask bit which can be written to 0 or 1 (1 to enable an interrupt) interrupt request flag which is set on the input rising edge timer irq flag intte and prescaler irq flag intpr arrive independent of their mask bits not to loose any timing information. but the surfhvvruzlooehlqwhuuxswhgrqo\zlwkpdvnvhwwr EM6605 ? em microelectonic-marin sa, 02/99, rev. b/243 21 10. supply voltage level detector (svld) the EM6605 has a software configurable built-in supply voltage level detector. three levels can be defined between vddmin + 100mv and vddmax - 1000mv in steps of 100mv. during sleep mode this function is disabled. the required voltage compare level is selected by writing the bits vlc1 and vlc2 in the svld control register which also activates the compare measurement. since the measurement is not immediate the busy flag remains high during the measurement and is automatically cleared low when the measurement is finished. the result is indicated by inspection of the vldr flag. if the result is 0 then the voltage level is higher than the selected compare level. and if 1 is lower than the compare level. the result vldr of the last measurement remains until the new one is started. the start of a new measurement resets the vldr (svld result bit) to 0. during the svld operation power consumption increases by approximately 3 $ gxulqj rqh shulrg ri ck[9] (~3.9msec with *f1 ). the measurement internally starts with the rising ck[9] edge following the svld test command. the additional svld consumption stops after the falling edge of the ck[9] internal clock. table 33 lists the possible voltage levels table 33.svld level selection evaluation voltage vlc1 vlc0 not active 0 0 vl1 (low level) 0 1 vl2 1 0 vl3 (high level) 1 1 10.1. svld register table 34.svld control register - svld bit name reset r/w description 3 vldr 0 r svld result (0=higher 1=lower) 2 busy 0 r measurement in progress 1 vlc1 0 r/w svld level control 1 0 vlc0 0 r/w svld level control 0 EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 22 11. serial (output) write buffer - swb the EM6605 has simple serial write buffer ( swb ) which outputs serial data and serial clock. the swb is enabled by setting the bit v03 in the clkswb register as well as setting port d to output mode. the combination of the possible portd mode is shown in table 357. in swb mode the serial clock is output on port d0 and the serial data is output on port d1. the signal testvar[3], which is used by the processor to make conditional jumps, indicates "transmission finished" in automatic send mode or "swbbuffer empty" in interactive send mode. in interactive mode, testvar[3] is equivalent to the interrupt request flags stored in intrq register : it permits to recognize the interrupt source. (see also the interrupt handling section 9.interrupt controller for further information). to serve the "swbbuffer empty " interrupt request, one only has to make a conditional jump on testvar[3]. the serial write buffer output clock frequency is selected by bits clkswb0 and clkswb1 in the clkswb register. the possible values are 1khz (default), 2khz, 8khz or 16khz and are shown in table 35. table 36.swb clock selection swb clock output ckswb1 ckswb0 ck[11]; (= 1 024 hz *f1 ) 0 0 ck[12]; (= 2 048 hz *f1 ) 0 1 ck[14]; (= 8 192 hz *f1 ) 1 0 ck[15]; (= 16 348 hz *f1 ) 1 1 table 376.swb clock selection register - clkswb bit name reset r/w description 3 v03 0 r/w serial write buffer selection 2 - 0 r reserved - read 0 1 ckswb1 0 r/w swb clock selector 1 0 ckswb0 0 r/w swb clock selector 0 table 387.portd status portd status ciopd v03 pd0 pd1 pd2 pd3 ? normal ? 0 0 input input input input ? normal ? 0 1 input input input input ? normal ? 1 0 output pd0 output pd1 output pd2 output pd3 ? swb ? 1 1 serial clock out swb serial data output pd2 output pd3 when the swb is enabled by setting the bit v03 testvar[3], which is used to make conditional jumps, is reassigned to the swb and indicates either "swbbuffer empty " interrupt or "transmission finished" . after power-on-reset v03 is cleared at "0" and testvar[3] is consequently assigned to pa2 input terminal. the swb data is output on the rising edge of the clock. consequently, on the receiver side the serial data can be evaluated on falling edge of the serial clock edge. EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 23 figure 12.serial write buffer table 39.swb buffer register - swbuff bit name reset r/w description 3 buff3 1 r/w swb buffer d3 2 buff2 1 r/w swb buffer d2 1 buff1 1 r/w swb buffer d1 0 buff0 1 r/w swb buffer d0 table 40.swb low size register - lowswb bit name reset r/w description 3 size[3] 0 r/w auto mode buffer size bit3 2 size[2] 0 r/w auto mode buffer size bit2 1 size[1] 0 r/w auto mode buffer size bit1 0 size[0] 0 r/w auto mode buffer size bit0 table 41.swb high size register - highswb bit name reset r/w description 3 autoswb 0 r/w swb automatic mode select 2 stswb 0 r/w swb start interactive mode 1 size[5] 0 r/w auto mode buffer size bit5 0 size[4] 0 r/w auto mode buffer size bit4 the swb has two operational modes, automatic mode and interactive mode. EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 24 11.1. swb automatic send mode automatic mode enables a buffer on a predefined length to be sent at high transmission speeds up to ck[15] (16khz *f1 ). in this mode user prepares all the data to be sent (minimum 8 bits, maximum 256 bits) in the ram. the user then selects the clock speed, sets the number of data nibbles to be sent, selects automatic transmission mode ( autoswb bit set to 1) and enters standby mode by executing a halt instruction. once the halt instruction is activated the swb peripheral module sends the data in register swbuff followed by the data in the ram starting at address 00 up to the address specified by the bits size[5:0 ] located in the lowswb, highswb registers. during automatic transmission the general inten bit is disabled automatically to prevent other interrupts to reset the standby mode. at the end of automatic transmission em6603 leaves standby mode ( inten is automatically enabled) and sets testvar[3] high. testvar[3] = 1 is signaling swb transmission is terminated. as soon as swbauto is high, the general inten flag is disabled until the swbauto goes back low. after automatic swb transmission inten bit becomes active high. although set to 1 via the halt instruction the bit inten is disabled throughout the whole swb automatic transmission. it resumes to 1 at the end of transmission . the data to be sent must be prepared in the following order: first nibble to be sent must be written in the swbuff register . the other nibbles must be loaded in the ram from address 0 (second nibble at adr.0, third at adr.1,...) up to the address with last nibble of data to be send = "size" address. max. address space for swb is 3e ("size" 3e hex) what gives with swbuff up to 64 nibbles (256 bits) of possible data to be sent. the minimum possible data length we can send in automatic swb mode is 8 bits when the last ram address to be sent is 00 ("size" = 00) once data are ready in the ram and in the swbuff , user has to load the "size" (adr. of the last nibble to be send - bits size[5:0] ) into the lowswb and highswb register together with autoswb bit = 1. now everything is ready for serial transmission. to start the transmission one has to put the em6603 in standby mode with the halt instruction. with this serial transmission starts. when transmission is finished the testvar[3] (can be used for conditional jumps) becomes active high, the autoswb bit is cleared, the processor is leaving the standby mode and inten is switched on. figure 13.automatic serial write buffer transmission EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 25 the processor now starts to execute the first instruction placed after the halt instruction (for instance write of swbuff register to clear testvar[3]), except if there was a irq during the serial transmission. in this case the cpu will go directly in the interrupt routine to serve other interrupt sources. testvar[3] stays high until swbuff is rewritten. before starting a second swb action this bit must be cleared by performing a dummy write on swbuff address. because the data in the ram are still present one can start transmitting the same data once again only by recharging the swbuff , lowswb and highswb register together with autoswb bit and putting the em6603 in halt mode will start new transmission. EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 26 11.2. swb interactive send mode in interactive swb mode the reloading of the data transmission register swbbuff is performed by the application program. this means that it is possible to have an unlimited length transmission data stream. however, since the application program is responsible for reloading the data a continuous data stream can only be achieved at ck[11] or ck[12] (1khz or 2khz *1 ) transmission speeds. for the higher transmission speeds a series of writes must be programmed and the serial output clock will not be continuous. serial transmission using the interactive mode is detailed in figure 14. programming of the swb in interactive is achieved in the following manner: select the transmission clock speed using the bits clksw0 and clksw1 in the clkswb register. load the first nibble of data into the swb data register swbbuff start serial transmission by selecting the bit stswb in the register highswb register. once the data has been transferred into the serial transmission register a non maskable interrupt (swbempty) is generated and testvar[3] goes high. the cpu goes in the interrupt routine, with the jpv3 as first instruction in the routine one can immediately jump to the swb update routine to load the next nibble to be transmitted into the swbuff register. if this reload is performed before all the serial data is shifted out then the next nibble is automatically transmitted. this is only possible at the transmission speeds of ck[11] or ck[12] (1khz or 2khz *1 ) due to the number of instructions required to reload the register. at the higher transmission speeds of ck[14] or ck[15] (8khz and 16khz *1 ) the application must restart the serial transmission by writing the stswb in the high swbhigh register after writing the next nibble to the swbbuff register. each time the swbuff register is written the "swbbuffer empty interrupt" and testvar[3] are cleared to "0". for proper operation the swbuff register must be written before the serial clock drops to low during sending the last bit (msb) of the previous data. figure 14.interactive serial write buffer transmission after loading the last nibble in the swbbuff register a new interrupt is generated when this data is transferred to an intermediate shift register. precaution must be made in this case because the swb will give repetitive interrupts until the last data is sent out completely and the stswb bit goes low automatically. one possibility to overcome this is to check in the interrupt subroutine that the stswb bit went low before exiting interrupt. be careful because if stswb bit is cleared by software transmission is stopped immediately. at the end of transmission a dummy write of swbuff must be done to clear testvar[3] and "swbbuffer empty interrupt" or the next transmission will not work. EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 27 12. strobe / reset output the stb/rst output pin is used to indicate the EM6605 reset condition as well as write operations to ports b, c and d. for a portb, portc and portd write operation the strobe signal goes high for half of the system clock period. write is effected on falling edge of the strobe signal and it can this be used to indicate when data changes at the output port pins. in addition, any EM6605 internal reset condition is indicated by a continuous high level on stb/res for the period of the reset. 13. test at em - active supply current test for this purpose, five instructions at the end of the rom will be added. testloop : ;reset watchdog here sti 00h, 05h ;test loop sti 75h 0ah ldr 00a ldr 75h jmp testloop 14. metal mask options the following options can be selected at the time of programming the metal mask rom. table 42 buzzer frequecies description basic (hi) reduced (lo) ck[buz1] 1st buzzer frequency ck[buz2] 2nd buzzer frequency put one cross in each line EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 28 table 43 input/output ports pull-up y es / n o pull-down y es / n o nch-open drain y es / n o input blocked when output y es / n o output hi-z in sleep mode y es / n o 0 1 4 5 * 1 6 * 2 a0 pa0 input a1 pa1 input a2 pa2 input a3 pa3 input b0 pb0 in/out b1 pb1 in/out b2 pb2 in/out b3 pb3 in/out c0 pc0 in/out c1 pc1 in/out c2 pc2 in/out c3 pc3 in/out d0 pd0 in/out d1 pd1 in/out d2 pd2 in/out d3 pd3 in/out put one letter (y, n, r, f)in each box from proposed for the column. *1 port wise for portc and portd (one possibility for the whole port); portb bit-wise *2 port-wise for portc and portd (one possibility for the whole port); portb bit-wise table 44 porta reset option - one option must be selected no porta reset combination pa0 & pa1 logic and input reset pa0 & pa1 & pa2 logic and input reset pa0 & pa1 & pa2 & pa3 logic and input reset 0 1 2 3 ra porta reset table 45 svld levels C see 16.6 dc characteristics Csv detector levels C write typ. value of used levels typ. vl1 level [v] typ. vl2 level [v] typ. vl3 level [v] vl svld level in volts targeted frequency is : _____________ khz software name is : ______________ .bin, dated ______________ the customer should specify the required options at the time of ordering. a copy of this sheet, as well as the ? software rom characteristic file ? generated by the assembler (*.sta) should be attached to the order. EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 29 15. peripheral memory map the following table shows the peripheral memory map of the EM6605. the address space is between $00 and $7f (hex). any addresses not shown can be considered to be reserved. register name add hex add dec power up value write_bits read_bits remarks b'3210 read/write_bits ram 00- 5f 0-95 xxxx 0: d0 1: d1 2: d2 3: d3 direct addressing ltimls 60 96 0000 0: tl0 1: tl1 2: tl2 3: tl3 0: ts0 1: ts1 2: ts2 3: ts3 low nibble of 8bit timer load and status register htimls 61 97 0000 0: tl4 1: tl5 2: tl6 3: tl7 0: ts4 1: ts5 2: ts6 3: ts7 high nibble of 8bit timer load and status register timctr 62 98 0000 0: tec0 1: tec1 2: tec2 3:timauto timer control register with frequency selector option 63 99 0000 0: nowd 1: debpan 2: debpcn 3:irqedger option register pa3cnt 65 101 xxx0 0: pa3cntin 1: - 2: - 3: - pa3 counter input clkswb 68 104 0000 0: ckswb0 1: ckswb1 2: - 3: v03 clock selector for swb swbuff 69 105 1111 0: buff0 1: buff1 2: buff2 3: buff3 swb intermediate buffer lowswb 6a 106 0000 0: size[0] 1: size[1] 2: size[2] 3: size[3] low nibble to define the size of data to be send in automatic mode highswb 6b 107 0000 0: size[4] 1: size[5] 2: stswb 3:autoswb the size of the data to be sent & swb control svld 6c 108 0000 0: vlc0 1: vlc1 2: - 3: - 0: vlc0 1: vlc1 2: busy 3: vldr voltage level detector control cirqd 6d 109 xx00 0: inten 1: debck 2: - 3: - global interrupt enable debouncer clock index low 6e 110 xxxx internally used for index register index high 6f 111 xxxx internally used for index register EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 30 register name add hex add dec power up value write_bits read_bits remarks b'3210 read/write_bits intrq 70 112 0000 0: - 1: - 2: sleep 3: - 0: intpa 1: intpc 2: intte 3: intpr interrupt requests sleep mode wd 71 113 0000 0: - 1: - 2: slmask 3: wdrst 0: wd0 1: wd1 2: slmask 3: 0 watchdog timer control and sleep mask porta 72 114 xxxx 0: pa0 1: pa1 2: pa2 3: pa3 port a status irqpa 73 115 0000 0: irqpa0 1: irqpa1 2: irqpa2 3: irqpa3 port a interrupt request mporta 74 116 0000 0: mpa0 1: mpa1 2: mpa2 3: mpa3 port a mask portb 75 117 xxxx 0: pb0 1: pb1 2: pb2 3: pb3 port b input/output cioportb 76 118 0000 0: ciopb0 1: ciopb1 2: ciopb2 3: ciopb3 port b input/output individual control portc 77 119 xxxx 0: pc0 1: pc1 2: pc2 3: pc3 port c input/output irqpc 78 120 0000 0: irqpc0 1: irqpc1 2: irqpc2 3: irqpc3 port c interrupt request mportc 79 121 0000 0: mpc0 1: mpc1 2: mpc2 3: mpc3 port c mask portd 7a 122 xxxx 0: pd0 1: pd1 2: pd2 3: pd3 port d input/output cpiob 7c 124 x000 0: pa&c 1: ciopc 2: ciopd 3: - portairq and portcirq portc in/out portd in/out presc 7d 125 0000 0: psf0 1: psf1 2: prst 3: mtim 0: psf0 1: psf1 2: 0 3: mtim prescaler control timer mask beep 7e 126 0000 0: bcf0 1: bcf1 2: buen 3: timen buzzer control timer enable regtestem 7f 127 ---- ---- ---- reserved EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 31 16. measured electrical behaviors 16.1. idd current specially the stand-by current ( i vddh) depends on the current mirror ratio between the current which goes through an external resistor ( i rext) and the current which is used in the internal rc oscillator capacitor ( i rcint). like that we can reduce the power consumption in standby mode. this current is approximately equal to: i r ext ~ 0.2v / rext the internal oscillator capacitor is charged with 1/5,1/4,1/3, or 1/2 of this current. all data here are with ratio i rcint / i rext = 1/5. i vdda[a] ~ i vddh + f[khz]*0.067 i(vdda) active = f(freq), vdd=3v 4 8 12 16 20 24 28 0 50 100 150 200 250 300 [khz] [ua] i(vdda) active, vdd=3.0/5.0v,r=330kohm 5.0 6.0 7.0 8.0 -40-200 20406080 [c] [ua] 3v 5v i(vddh) active, vdd=3.0v,r=120kohm 16.0 17.0 18.0 19.0 -40-20 0 20406080 [c] [ua] 5v 3v i(vddh) standby = f(freq), vdd=3v 0 1 2 3 4 5 6 0 50 100 150 200 250 300 [khz] [ua] i(rext) @ x=1/5 i(vddh) standby, vdd =3.0/5.0v,rext=330kohm 2 2.2 2.4 2.6 2.8 -40-20 0 20406080 [c] [ua] 3v 5v i(vddh) standby, vdd =3.0/5.0v,rext=120kohm 3.8 4 4.2 4.4 -40-200 20406080 [c] [ua] 5v 3v i(vdds) sleep mode, vdd=3v/5v 290 310 330 350 -40-20 0 20406080 [c] [na] 5v 3v current ratio i (rcint) / i (rext) frequency x = 1/5 f = f0 x = 1/4 f = f0 * 1.25 x = 1/3 f = f0 * 1.67 x = 1/2 f = f0 * 2.50 EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 32 16.2. frequency last table on previous page shows already that we can adjust the frequency tw. needed resistor also with different current mirror i rcint / i rext. please contact em marin directly when ordering EM6605 if you would like to profit this possibility. next figures show the frequency dependence on rext when i rcint / i rext = 1/5 16.3. regulated voltage vreg @vdd=3.0v 2.0 2.1 2.2 2.3 2.4 -40-20 0 20406080 [c] [v] vreg @ temp = 25c 1.7 1.9 2.1 2.3 2.5 1.5 2.5 3.5 4.5 vdd [v] freq = f(t), vdd=3.0v, (rext=329kohm*) 50.0 60.0 70.0 80.0 -40-20 0 20406080 [c] [khz] freq = f(t), vdd=3.0v, (rext=240kohm*) 80.0 90.0 100.0 110.0 -40 -20 0 20 40 60 80 [c] [khz] freq = f(t), vdd=3.0v, (rext=120kohm*) 180.0 190.0 200.0 210.0 220.0 -40-20 0 20406080 [c] [khz] freq = f(t), vdd=3.0v, (rext=82kohm*) 280.0 290.0 300.0 310.0 320.0 -40-20 0 20406080 [c] [khz] freq = f(rext*) @25c 50 100 150 200 250 300 350 80.0 130.0 180.0 230.0 280.0 330.0 [kohm] [khz] EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 33 16.4. output currents iol portb; vds=0.3/0.5; @ t=25c 0 4 8 12 16 20 24 1.8 2.8 3.8 4.8 [v] [ma] 0.5v ioh portb; vds=0.3/0.5; @t=25c -16 -14 -12 -10 -8 -6 -4 -2 0 1.8 2.8 3.8 4.8 [v] [ma] 0.3v iol portb; vdd=3.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 10 20 30 40 50 -40-20 0 20406080[c] [ma] iol portb; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 10 20 30 40 50 -40-20 0 20406080[c] [ma] ioh portb; vdd=3.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -40 -30 -20 -10 0 -40-20 0 20406080 [c] [ma] ioh portb; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -40 -30 -20 -10 0 -40-20 0 20406080 [c] [ma] iol portc,stb/rst; vdd=3.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 1 2 3 4 5 -40-20 0 20406080[c] [ma] ioh portc,stb/rst; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -4 -3 -2 -1 0 -40-20 0 20406080 [c] [ma] EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 34 output currents C continued iol portc,stb/rst; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 1 2 3 4 5 -40-20 0 20406080 [c] [ma] iol portd; vdd=3.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 1 2 3 4 5 -40 -20 0 20 40 60 80 [c] [ma] iol portd; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 0 1 2 3 4 5 -40-20020406080 [c] [ma] ioh portc,stb/rst; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -5 -4 -3 -2 -1 0 -40 -20 0 20 40 60 80 [c] [ma] ioh portd; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -5 -4 -3 -2 -1 0 -40-20 0 20406080 [c] [m a] ioh portd; vdd=5.0v; vds=0.3/0.5/1.0v 1.0 0.3 0.5 -5 -4 -3 -2 -1 0 -40-20 0 20406080 [c] [ma] EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 35 16.5. pull up / down resistors pull-up/down porta,c,d; vdd=3.0v 15 35 55 75 95 115 135 155 175 195 215 235 -40-20 0 20406080 [c] [kohm] optm opth optl pull-up/down portb; vdd=3.0v 15 35 55 75 95 115 135 155 175 195 215 235 255 275 295 -40-20 0 20406080 [c] [kohm] opth optm optl pull-down reset, test; vdd=3.0v 10 30 50 70 90 110 130 -40 -20 0 20 40 60 80 [c] [kohm] reset test EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 36 17. electrical specifications 17.1. absolute maximum ratings min. max. unit supply voltage vdd-vss - 0.2 + 6.0 v input voltage vss - 0.2 vdd+0.2 v storage temperature - 50 + 125 c stresses above these maximum ratings may cause permanent damage to the device. exposure beyond specified electrical characteristics may affect device reliability or cause malfunction . 17.2. standard operating conditions parameter value description temperature -40c...+85c vdd (fmax. = 200khz) +1.8 ...+5.5v with internal voltage regulator vdd (fmax. = 300khz) +2.4 ...+5.5v with internal voltage regulator vss 0 v (reference) cvreg min. 100nf regulated voltage capacitor tow. vss rext (typical) 120k w - 330k w external resistor to set frequency 17.3. handling procedures this device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 17.4. dc characteristics - power supply vdd=3.0v, t=25c, rext ? 120k w (note4) (unless otherwise specified), f ? 200khz, i rcint / i rext = 1/5 parameter conditions symb. min. typ. (note1) max. unit active supply current (note2) i vdda 17.0 22.0 a active supply current (in active mode) (note2) (note3) -40c...+85c i vdda 25.0 a standby supply current i vddh 4.1 6.0 a standby supply current (in halt mode) (note3) -40c...+85c i vddh 8.0 a sleep supply current i vdds 0.3 0.5 a sleep supply current (sleep =1) (note3) -40c...+85c i vdds 2.0 a por voltage v por 0.9 1.4 v ram data retention vrd 1.5 v regulated voltage vreg not at vdd vreg 1.8 2.2 2.6 v note: pieces are tested with fixed resistors between 330k w and 120k w at the frequency used by the customer. EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 37 note1: for current measurement the corresponding resistor for targeted frequency 20% is selected; all i/o pins without internal pull up/down are pulled to vdd externally. note2: test loop with successive writing and reading of two different addresses with an inverted values (five instructions should be reserved for this measurement), note3: not tested if delivered in chip form. note4: test conditions for active and standby supply current mode are: external resistor between the rcin and vss pins. 17.5. dc characteristics - in/out pins -40c EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 41 19. packages figure 16. dimensions of dip24 package C package type a p-dip24 .300 inch body width EM6605 ? em microelectronic-marin sa, 02/99, rev. b/243 42 figure 17. dimensions of tssop24 package C package type f tssop24 (0.65mm pitch, 4.4mm body width) figure 18.dimensions of soic24 package C package type b (1.27mm pitch, 300mils body width) sop-24 visual control on wafer: aql = 0.4% for all visual defects. EM6605 ? em microelectonic-marin sa, 2/99, rev. b/243 em microelectronic-marin sa ch-2074 marin, switzerland, tel. +41 32 755 51 11, fax. +41 32 755 54 03 43 20. chip marking : independent on the package there is always marking EM6605 followed by the: version number given by em microelectronic marin production identification given by em microelectronic marin customer marking selected by customer (letters, numbers, -, empty space) 20.1. customer marking : there are 11 digits available for customer marking on dip24 and soic24 . there are 4 digits available for customer marking on tssop24 . 21. ordering information : 21.1. packaged device ordering EM6605 vvv p f vvv = version - project specific given from em marin to customer (number from 001 C 999) p is for package type: f is for delivery form a = pdip a = stick - (for package a,b or f) b = soic b = eia reel - (for package b only) f = tssop 21.2. die form ordering EM6605 vvv df th b vvv = version - project specific given from em marin to customer (number from 001 C 999) df is for die form th is for thickness wa = wafer 08 = 8 mils (203 m m) sw = sawn wafer/frame 11 = 11 mils (280 m m) (standard if backlapped) wp = waffle pack 15 = 15 mils (380 m m) st = sticky tape 21 = 21 mils (533 m m) b is for bumps 27 = 27 mils (686 m m, not backlapped) a = without bumps b = with bumps please contact em headquarters or your local em office for any other detail. previous revision was, rev.a/152, 11/98 |
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